Exemplary embodiments of the present invention relate to semiconductor device fabrication technology, and more particularly, to a 3-dimensional (3D) nonvolatile memory device and a method for fabricating the same.
A non-volatile memory device refers to a memory device which maintains data stored therein even though power supply is cut off. As an increase in integration degree of 2-dimensional (2D) memory devices, in which memory cells are formed as a single layer on a substrate, approaches the limit, 3D nonvolatile memory devices in which memory cells are vertically stacked on a substrate have been proposed.
FIGS. 1A and 1B are perspective view of a conventional 3D nonvolatile memory device.
Referring to FIG. 1A, the conventional 3D nonvolatile memory device includes a plurality of channel structures C extending in parallel to each other and in a first direction I-I′, a plurality of memory cells MC stacked along a sidewall of the channel structure C, and a word line WL coupled to gate electrodes of the memory cells MC arranged in a second direction II-II′.
The channel structure C includes a plurality of interlayer dielectric layers 11 and channel layers 12 which are alternately stacked on a substrate 10, and the plurality of memory cells MC are stacked along the sidewall of the channel structure C. Each memory cell MC includes a memory layer 13 and a gate electrode 14 which are sequentially stacked on the channel layer 12. At this time, the memory layer 13 includes a tunnel insulation layer 13A, a charge trap layer 13B, and a charge block layer 13C which are sequentially stacked.
Referring to FIG. 1B, the conventional 3D nonvolatile memory device includes a plurality of drain selection lines DSL_0 to DSL_X, a plurality of drain contact plugs DCT_0 to DCT_X, and a plurality of bit lines BL. Hereafter, a conventional method for forming the drain selection lines DSL_0 to DSL_X, the drain contact plugs DCT_0 to DCT_X, and the bit lines BL is described.
First, a drain selection transistor region of the channel structure C is etched in a stepped shape to expose the plurality of channel layers 12, and gate dielectric layers 15 are formed on the exposed channel layers 12. Conductive layers for a gate electrode are formed on the gate dielectric layers 15, respectively, to form a plurality of drain selection transistors, and the plurality of drain selection lines DSL_0 to DSL_X are formed to couple the drain selection transistors arranged in the second direction, while extending in parallel to each other and in the second direction.
Accordingly, the flat drain selection transistors are formed on the plurality of channel layers 12, respectively. The drain selection transistors which are formed on the channel layers 12 at the same step level and arranged in the second direction are coupled by any one of the drain selection lines DSL_0 to DSL_X.
An insulation layer which is not illustrated in FIG. 1B is formed on the entire surface of the resultant structure, and a plurality of drain contact holes are formed to expose the surfaces of the respective channel layers 12. A conductive layer is buried in the drain contact holes to form the drain contact plugs DCT_0 to DCT_X coupled to the plurality of channel layers 12, respectively. The plurality of bit lines BL are formed to extend in parallel to each other and in the first direction, while coupled to the drain contact plugs DCT_0 to DCT_X.
In accordance with the conventional method, the channel structure C is patterned in a stepped shape to expose the plurality of channel layers 12, and the flat drain selection transistors are formed on the exposed channel layers 12, respectively. Therefore, a considerably large area is occupied for forming the flat drain selection transistors. Accordingly, although the number of channel layers 12 to be stacked is increased, there is a limitation in increasing the integration degree of the memory device, because the area for the drain selection transistors is accordingly increased. Furthermore, when the flat drain selection transistors are formed, it is highly likely that leakage current occurs. Therefore, the property of the memory device is degraded.
In accordance with the conventional method, the drain selection lines DSL_0 to DSL_X are arranged as plural layers. Therefore, during the fabrication process, a plurality of masks are to be used. Accordingly, a fabricating cost may increase, and there may be technical difficulties in patterning the respective drain selection lines DSL_0 to DSL_X.
Furthermore, the drain selection lines DSL_0 to DSL_X are used as the gate electrodes of the drain selection transistors, and formed of a polysilicon layer in consideration of a junction property with the gate dielectric layers 15. Here, in order to improve a signal transmission property of the memory device, the resistance of the drain selection lines DSL_0 to DSL_X is to be reduced. However, there is a limitation in reducing the resistance of the drain selection lines DSL_0 to DSL_X formed of a polysilicon layer. For reference, when the drain selection lines DSL_0 to DSL_X are formed of a low-resistance metallic layer such as a metal layer or a metal silicide layer in order to reduce its resistance, the drain selection lines DSL_0 to DSL_X are directly in contact with the gate dielectric layers 15 of the drain selection transistors, which may cause a malfunction of the drain selection transistors.